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PRELIMINARY
CY7C1001 CY7C1002
Features
D D D D D D D D
High speed tAA = 12 ns Transparent write (7C1001) CMOS for optimum speed/power Low active power 910 mW Low standby power 275 mW 2.0V data retention (optional) 100
W
Automatic power down when deselected TTL compatible inputs and outputs
The CY7C1001 and CY7C1002 are high performance CMOS static RAMs orga nized as 262,144 x 4 bits with separate I/O. Easy memory expansion is provided by ac tive LOW chip enable (CE) and three state drivers. Both devices have an auto matic power down feature, reducing the power consumption by more than 65% when deselected. Writing to the device is accomplished by taking both chip enable (CE) and write en able (WE) inputs LOW. Data on the four input pins (I0 through I3) is written into the memory location specified on the address pins (A0 through A17). Reading the device is accomplished by tak ing chip enable (CE) LOW while write en
I0 I1
Functional Description
256K x 4 Static RAM with Separate I/O able (WE) remains HIGH. Under these
conditions, the contents of the memory lo cation specified on the address pins will ap pear on the four data output pins (O0 through O3). The data output pins on the CY7C1001 and the CY7C1002 are placed in a high impedance state when the device is dese lected (CE HIGH). The CY7C1002's out puts are also placed in a high impedance state during a write operation (CE and WE LOW). In a write operation on the CY7C1001, the output pins will carry the same data as the inputs after a specified delay. The CY7C1001 and CY7C1002 are avail able in standard 300 mil wide DIPs and SOJs.
DIP/SOJ Top View
Logic Block Diagram
Pin Configuration
I2 I3
NC A16 A17 A0 A1 A2 A10 A11 A12 A13 A14 A9 I3 I2 CE GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 7C1001 7C1002
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC A15 A3 A4 A5 A6 A7 A8 NC I0 I1 O0 O1 O2 O3 WE
C1001-2
INPUT BUFFER
A2 A3 A4 A5 A6 A7 A8
SENSE AMPS
A1
ROW DECODER
A0
O0 O1
512 x 512 x 4 ARRAY
O2 O3
COLUMN DECODER
POWER DOWN
A 12
A 13
A 14
A 15
A 16
A 17
A10
A11
A9
CE
7C1002 ONLY
WE
7C1001 ONLY
C1001-1
Selection Guide
7C1001-12 7C1001-15 7C1002-15 7C1001-20 7C1002-20 7C1001-25 7C1002-25
Maximum Access Time (ns) Maximum Operating Current
7C1002-12
Commercial Military Maximum Standby Current (mA) Commercial Military
Cypress Semiconductor Corporation
12 165 50
15 155 165 40 40
20 140 150 30 30
25 130 140 30 30
D
3901 North First Street 1
D
San Jose
D
CA 95134 D 408-943-2600 November 1991 - Revised April 1995
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature . . . . . . . . . . . . . . . . . . -65_C to +150_C Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . . . . . . . -55_C to +125_C Supply Voltage on VCC Relative to GND[1] . -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] . . . . . . . . . . . . . . . . . . -0.5V to VCC + 0.5V DC Input Voltage[1] . . . . . . . . . . . . . . . . -0.5V to VCC + 0.5V Current into Outputs (LOW) . . . . . . . . . . . . . . . . . . . . . 20 mA
CY7C1001 CY7C1002
Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . . . >2001V (per MIL STD 883, Method 3015) Latch Up Current . . . . . . . . . . . . . . . . . . . . . . . . . . . >200 mA
Operating Range
Range
Commercial Military
Ambient Temperature[2]
0_C to + 70_C -55_C to + 125_C
VCC
5V 10% 5V 10%
Electrical Characteristics Over the Operating Range
Parameter
VOH VOL VIH VIL IIX IOZ IOS ICC
[3]
Description
Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1]
Test Conditions
VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA
7C1001-12 7C1001-15 7C1001-20 7C1001-25 7C1002-12 7C1002-15 7C1002-20 7C1002-25 Min. Max. Min. Max. Min. Max. Min. Max. Unit
2.4 0.4 2.2 -0.3 -1 -5 VCC + 0.3 0.8 +1 +5 -300 2.2 -0.3 -1 -5 2.4 0.4 VCC + 0.3 0.8 +1 +5 -300 155 165 50 40 40 2 2 2 2.2 -0.3 -1 -5 2.4 0.4 VCC + 0.3 0.8 +1 +5 -300 140 150 30 30 2 2 2.2 -0.3 -1 -5 2.4 0.4 VCC + 0.3 0.8 +1 +5 -300 130 140 30 30 2 2 mA mA V V V V
Input Load Current GND < VI < VCC Output Leakage Current Output Short Circuit Current[4] VCC Operating Supply Current Automatic CE Power Down Current TTL Inputs Automatic CE Power Down Current C t CMOS Inputs
[5]
GND < VI < VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA mA, f = fMAX = 1/tRC Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V , VIN > VCC - 0.3V 0 3V or VIN < 0.3V, f=0 Com'l Mil Com'l Mil Com'l Mil
mA mA
mA mA
165
ISB1
ISB2
Capacitance
Parameter
Description
Input Capacitance p p Output Capacitance
Test Conditions
TA = 25_C, f = 1 MHz, , , VCC = 5.0V 5 0V
Max.
7 10 10
Unit
pF pF pF
CIN: Addresses CIN: Controls COUT
1. 2. 3.
Notes:
VIL (min.) = -2.0V for pulse durations of less than 20 ns. TA is the instant on" case temperature. See the last page of this specification for Group A subgroup testing in formation.
4. 5.
Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. Tested initially and after any design or process changes that may affect these parameters.
2
PRELIMINARY
AC Test Loads and Waveforms
R1 480W 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 255W INCLUDING JIG AND SCOPE 5V OUTPUT 10% 5 pF R2 255W GND < 3 ns R1 480W 3.0V 90%
CY7C1001 CY7C1002
ALL INPUT PULSES 90% 10%
< 3 ns
(a)
Equivalent to: THEVENIN EQUIVALENT 167W OUTPUT 1.73V
(b)
C1001-3
C1001-4
Switching Characteristics Over the Operating Range[3, 6]
7C1001-12 7C1002-12 Parameter READ CYCLE
tRC tAA tOHA tACE tLZCE tHZCE tPU tPD Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid CE LOW to Low Z
[7]
7C1001-15 7C1002-15 Min. Max.
7C1001-20 7C1002-20 Min. Max.
7C1001-25 7C1002-25 Min. Max. Unit
Description
Min.
Max.
12 12 3 12 3 6 0 12
15 15 3 15 3 7 0 15
20 20 3 20 3 8 0 20
25 25 3 25 3 10 0 25
ns ns ns ns ns ns ns ns
CE HIGH to High Z[7, 8] CE LOW to Power Up CE HIGH to Power Down
WRITE CYCLE[9]
tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tDWE tDCE tADV Write Cycle Time CE LOW to Write End Address Set Up to Write End Address Hold from Write End Address Set Up to Write Start WE Pulse Width Data Set Up to Write End Data Hold from Write End WE HIGH to Low Z
[7]
12 10 10 0 0 10 7 0 3 6 12 12 12
15 12 12 0 0 12 8 0 3 7 15 15 15
20 15 15 0 0 15 10 0 3 8 20 20 20
25 20 20 0 0 20 15 0 3 10 25 25 25
ns ns ns ns ns ns ns ns ns ns ns ns ns
WE LOW to High Z[7, 8] WE LOW to Data Valid (7C1001) CE LOW to Data Valid (7C1001) Data Valid to Output Valid (7C1001)
Notes: 6. Test conditions assume signal transition time of 3 ns or less, timing ref erence levels of 1.5V input pulse levels of 0 to 3.0V and output loading , , of the specified IOL/IOH and 30 pF load capacitance.
7. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device. tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady state voltage.
9.
The internal write time of the memory is defined by the overlap of CE and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set up and hold timing should be referenced to the leading edge of the signal that terminates the write.
3
PRELIMINARY
Data Retention Characteristics
CY7C1001 CY7C1002
Over the Operating Range (L Version Only)
Commercial Military Min. Max. Units
Parameters
Description
Conditions
[10]
Min.
Max.
VDR ICCDR tCDR[5] tR
[5]
VCC for Retention Data Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = VDR = 2.0V , CE > VCC - 0.3V 0 3V , VIN > VCC - 0.3V or VIN < 0.3V
2.0 50 0 tRC
2.0 70 0 tRC
V
mA
ns ns
Note:
. 10. No input may exceed VCC + 0.5V
Data Retention Waveform
DATA RETENTION MODE VCC 4.5V tCDR 4.5V tR
VDR > 2V
CE
C1001-5
Switching Waveforms
Read Cycle No. 1
[11, 12]
tRC
ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
C1001-6
Read Cycle No. 2
[12, 13]
ADDRESS
tRC CE
tACE
tHZCE
HIGH IMPEDANCE
HIGH IMPEDANCE DATA OUT tLZCE tPU VCC SUPPLY CURRENT 50% 50% tPD DATA VALID
ICC
ISB
C1001-7
Notes:
11. Device is continuously selected, CE = VIL. 12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
4
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[9, 14]
tWC
CY7C1001 CY7C1002
ADDRESS
tSA
tSCE
CE tAW tPWE WE tHA
tSD DATA VALID
tHD
DATA IN
DATA OUT (7C1002)
HIGH IMPEDANCE tADV
tHZCE
DATA OUT (7C1001) tLZCE tDCE
DATA VALID
C1001-8
Write Cycle No. 2 (WE Controlled)[9]
tWC
ADDRESS
tSCE
CE tAW tSA WE tPWE tHA
tSD DATA IN DATA VALID
tHD
tHZWE DATA OUT (7C1002) tDWE DATA OUT (7C1001) tADV
tLZWE HIGH IMPEDANCE
tHZCE DATA VALID
C1001-9
Note: 14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state (7C1002 only).
5
PRELIMINARY
Truth Table
CE WE O0 - O3 Mode Power
CY7C1001 CY7C1002
H L L L
Note:
X H L L
High Z Data Out High Z Input Tracking
Power Down Read 7C1002: Standard Write 7C1001: Transparent Write[15]
Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
15. Outputs track inputs after specified delay.
Ordering Information
Speed (ns) Ordering Code Package Name Package Type Operating Range
12 15
CY7C1001-12PC CY7C1001-12VC CY7C1001-15PC CY7C1001-15VC CY7C1001-15DMB
P31 V32 P31 V32 D32 P31 V32 D32 P31 V32 D32
32 Lead (300 Mil) Molded DIP 32 Lead (300 Mil) Molded SOJ 32 Lead (300 Mil) Molded DIP 32 Lead (300 Mil) Molded SOJ 32 Lead (300 Mil) CerDIP 32 Lead (300 Mil) Molded DIP 32 Lead (300 Mil) Molded SOJ 32 Lead (300 Mil) CerDIP 32 Lead (300 Mil) Molded DIP 32 Lead (300 Mil) Molded SOJ 32 Lead (300 Mil) CerDIP
Commercial Commercial Military Commercial Military Commercial Military
20
CY7C1001-20PC CY7C1001-20VC CY7C1001-20DMB
25
CY7C1001-25DC CY7C1001-25VC CY7C1001-25DMB
Contact factory for L version availability. "
Speed (ns) Package Name Operating Range
Ordering Code
Package Type
12 15
CY7C1002-12PC CY7C1002-12VC CY7C1002-15PC CY7C1002-15VC CY7C1002-15DMB
P31 V32 P31 V32 D32 P31 V32 D32 P31 V32 D32
32 Lead (300 Mil) Molded DIP 32 Lead (300 Mil) Molded SOJ 32 Lead (300 Mil) Molded DIP 32 Lead (300 Mil) Molded SOJ 32 Lead (300 Mil) CerDIP 32 Lead (300 Mil) Molded DIP 32 Lead (300 Mil) Molded SOJ 32 Lead (300 Mil) CerDIP 32 Lead (300 Mil) Molded DIP 32 Lead (300 Mil) Molded SOJ 32 Lead (300 Mil) CerDIP
Commercial Commercial Military Commercial Military Commercial Military
20
CY7C1002-20PC CY7C1002-20VC CY7C1002-20DMB
25
CY7C1002-25PC CY7C1002-25VC CY7C1002-25DMB
Contact factory for L version availability. "
6
PRELIMINARY
MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics
Parameter Subgroups
CY7C1001 CY7C1002
VOH VOL VIH VIL Max. IIX IOZ ICC ISB1 ISB2
1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
Switching Characteristics
Parameter READ CYCLE Subgroups
tRC tAA tOHA tACE
7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11
WRITE CYCLE
tWC tSCE tAW tHA tSA tPWE tSD tHD tDWE[16] tADV[16]
Note:
16. 7C1001 only.
Document #: 38-00200-B
7
PRELIMINARY
Package Diagrams
32 Lead (300 Mil) CerDIP D32
CY7C1001 CY7C1002
32 Lead (300 Mil) Molded DIP P31
8
PRELIMINARY
Package Diagrams (continued)
32 Lead (300 Mil) Molded SOJ V32
CY7C1001 CY7C1002
E
Cypress Semiconductor Corporation, 1992. The information contained herein is subject to change without notice.
Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress Semiconductor Corporation product. Nor does it convey or imply any license under patent or other rights. Cypress Semicon ductor does not authorize its products for use as critical components in life support systems where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life support systems applications implies that the manufacturer assumes all risk of such use and in so doing indemnifies Cypress Semiconductor against all damages.
9

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